1. Field of the Invention
The present invention relates to a pattern for checking the alignment accuracy of a wiring pattern used in manufacturing a semiconductor device.
2. Description of the Related Art
In manufacturing a semiconductor device, a reduction projection exposure apparatus is used to pattern a photoresist film. At this time, a relative position between a certain pattern formed on a semiconductor substrate in the preceding process and a mask pattern formed on the photoresist film by the reduction projection exposure apparatus must be measured to calculate a misalignment amount. For example, when an aluminum wiring layer is to be patterned on an insulating interlayer having a contact hole, a photoresist is coated on the entire surface of the aluminum film and exposed, thereby leaving the photoresist in only a region subjected to patterning. At this time, the exposure position is determined in accordance with a mark provided on the substrate. However, even when alignment is performed with reference to the mark, the patterned photoresist is actually misaligned in some cases. Such misalignment cannot be detected in a region where an element such as a transistor is formed. Therefore, a region for detecting this misalignment is provided in addition to the area where the element such as a transistor is formed, and an alignment accuracy check pattern is formed in this region. The principle of detection of a misalignment amount will be described below with reference to FIG. 1.
Referring to FIG. 1, reference numerals 9-1, 9-2, 9-3, 9-4, and 9-5 (to be referred to as "9" hereinafter if any specific pattern need not be indicated) denote patterns formed on a substrate. Reference numerals 7-10, 7-11, 7-12, 7-13, and 7-14 (to be referred to as "7" hereinafter if any specific patterned photoresist need not be indicated) denote photoresists patterned on the patterns 9. Assume that the photoresists 7 have a pattern width L1 of 1.5 .mu.m, the patterns 9 have a pattern width L2 of 3.0 .mu.m, and a difference between a pattern pitch L3 of the photoresists 7 and a pattern pitch L4 of the patterns 9 is 0.05 .mu.m, i.e., L4=L3+0.05 .mu.m. In this case, the pattern pitch L3 of the photoresists 7 is shorter than the pattern pitch L4 of the patterns 9. Therefore, only one photoresist 7 has its central line matching with the central line of the corresponding pattern 9. FIG. 1 shows a case wherein only the central photoresist 7-12 has the central line matching with the central line of the corresponding pattern 9. In this case, misalignment is not detected. If the photoresist 7-13 has the central line matching with the central line of the corresponding pattern 9, misalignment in an amount of 0.05 .mu.m in the right direction is detected. Similarly, if the photoresist 7-14 has the central line matching with the central line of the corresponding pattern 9, misalignment in an amount of 0.1 .mu.m in the right direction is present.
A conventional alignment accuracy check pattern will be described below with reference to FIG. 2.
FIG. 2 is a sectional view showing a misalignment check pattern and corresponding to a sectional view taken along a line C-C' in FIG. 1 before patterning. Referring to FIG. 2, reference numeral 10 denotes a semiconductor substrate. A first insulating interlayer 20 consisting of a silicon oxide film or the like is used to insulate an element from a polysilicon wiring layer in an element formation region. In the element region, a first wiring layer consisting of polysilicon is formed on the first insulating interlayer 20. In a region used for an alignment accuracy check pattern, however, such a polysilicon wiring layer is not formed because no element such as a transistor is formed, as a matter of course. A second insulating interlayer 40 is used to insulate the polysilicon layer serving as the first wiring layer from an aluminum wiring layer 50 serving as a second wiring layer in the element region. Like the first insulating interlayer, the second insulating interlayer 40 consists of silicon oxide or the like. As described above, no polysilicon film serving as the first wiring layer is present in this region, so the second insulating interlayer 40 is directly formed on the first insulating interlayer 20. A contact hole 6 is formed in the first and second insulating interlayers 20 and 40. This contact hole 6 reaches the semiconductor substrate 10. The contact hole 6 corresponds to the pattern 9-2 in FIG. 1. In the element region, such a contact hole is formed to connect the first and second wiring layers with each other, so it is sufficient to etch only the second insulating interlayer 40. However, in formation of a contact hole, overetching is normally caused. That is, etching is continuously performed after the wiring layer immediately under the insulating interlayer 40 is etched because variations in thickness of the insulating interlayer must be taken into consideration. Of course, in the element region, even when overetching is performed to the wiring layer immediately under the insulating layer, the wiring layer is not etched. This is because the etching rate of the insulating interlayer has a large difference from that of the wiring layer. If a wiring layer is present, it serves as an etching stopper. However, since no wiring layer is formed in the region used for an alignment accuracy check pattern, as described above, the contact hole 6 reaches the semiconductor substrate 10, as shown in FIG. 2. In most popular anisotropic dry etching, almost all types of insulating layers have almost the same etching rate. For this reason, even if the first insulating interlayer 20 and the second insulating interlayer 40 do not consist of the same material, overetching is caused. In addition, the second wiring layer 50 consisting of aluminum is deposited on the entire surface of the chip with the contact hole 6, and the photoresist 7 is deposited on the entire surface of the second wiring layer 50. In this state, the exposure position is set in accordance with a mark, and exposure is then performed. The resist 7 is removed while leaving the mask portion, and a pattern having the central line of the contact hole 6 matching with that of the photoresist 7 is checked using a microscope or the like. With this operation, a misalignment amount between the pattern of the contact hole and the photoresist pattern used for patterning of the aluminum wiring layer can be detected on the order of 0.05 .mu.m.
Normally, in a semiconductor device, all contact hole portions in a region except for the alignment accuracy check pattern region are covered by the aluminum wiring layer, and no aluminum pattern is formed in the contact hole. Therefore, the exposure conditions of a reduction projection exposure apparatus may be set while only a thickness T.sub.2 of the photoresist in FIG. 2 is taken into consideration. On the other hand, in the alignment accuracy check pattern, a portion where the photoresist has a thickness T.sub.1 must be patterned to leave the pattern of the aluminum film 50 in the contact hole 6 in FIG. 2. However, since the contact hole 6 has a large depth as described above, the thickness T.sub.1 of the photoresist in the contact hole 6 becomes much larger than the thickness T.sub.2 outside the contact hole after the photoresist film is coated in the conventional alignment accuracy check pattern, as shown in FIG. 2. In this case, a standing-wave effect due to interference between incident light and reflected light appears because of the high reflectance of the aluminum film 50. This effect largely depends on the thickness of the resist. For this reason, when the thickness T.sub.2 changes to the thickness T.sub.1, the shape of the photoresist largely changes accordingly. In general, a photoresist having a smaller thickness can be more accurately patterned. Because of these influences, the photoresist film of the alignment accuracy check pattern has a largely tapered pattern shape, as indicated by the photoresist 7 in FIG. 3. FIG. 3 is a sectional view showing a case wherein the photoresist 7-11 is patterned to be slightly shifted in the right direction from the central line of the contact hole 6. FIG. 3 corresponds to the sectional view taken along the line C-C' in FIG. 1 after patterning and shows a portion where the thickness of the photoresist 7-11 is large, i.e., a state wherein the photoresist 7-11 is left in the contact hole 6. Assume that the misalignment amount of the photoresist film is to be checked by using the alignment accuracy check pattern having a shape shown in FIG. 3. As shown in FIG. 4, in all patterns (7-15 to 7-19), the photoresist tends to be left in the contact hole 6. For example, if the misalignment amount of the photoresist film 7 is 0.05 .mu.m in a X.sub.1 direction with respect to the contact hole 6, misalignment in the X.sub.1 direction can be detected from the appearance of the leftmost pattern. However, the remaining patterns appear to have the same misalignment amount, so the misalignment amount cannot be calculated. The conventional alignment accuracy check pattern poses the most serious problem when an upper wiring layer is to be aligned with a deep contact hole.